NDLI: A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm

Content Provider	Springer Nature Link
Author	Koranne, Sandeep
Copyright Year	2002
Abstract	In this paper a mathematical formulation and an efficient solution, of the embedded core-based system-on-chip (SOC) test scheduling problem (ECTSP) is presented. The ECTSP can be stated as follows; given a chip with N $_{C}$ cores each having a test T $_{i}$; where T $_{i}$ takes time $$F$$ to execute on a test access mechanism (TAM) of width w $_{j}$, and a constraint W on the number of top-level test pins; calculate the TAM assignment vector π and the schedule Σ for each test T $_{i}$, such that the completion time of the full chip test is minimized. All existing approaches have solved the ECTSP by solving the TAM partition and scheduling problem sequentially. In this paper we present an unified approach to solve the ECTSP. We present the first report of a design of reconfigurable core wrapper which allows for a dynamic change in the width of the test access mechanism (TAM) executing a core test. An automatic procedure for the creation of DfT hardware required for reconfiguration using a graph theoretic representation of core wrappers is also presented. For the case of reconfigurable wrappers, efficient algorithms to compute the schedule are presented based upon some recent results in the field of malleable task scheduling. Cases in which the degree of reconfigurability are constrained are considered; the case when only a single core can have reconfigurable wrapper, a schedule with zero TAM idle time can be found in time O(N $_{C}$(N $_{C}$ + W)lgW), and the case when only 2 different wrapper configurations are allowed can be solved in time O(N $_{C}$ $^{3}$). Comparison with existing results on benchmark SOCs show that our algorithms outperform state-of-art ILP formulations not only in schedule makespan, but also significantly reduce computation time.
Starting Page	415
Ending Page	434
Page Count	20
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	18
Issue Number	4-5
e-ISSN	15730727
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2002-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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