NDLI: A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

Content Provider	Springer Nature Link
Author	Wang, Baosheng Kuo, Andy Farahmand, Touraj Ivav, André Cho, Yong B. Tabatabaei, Sassan
Copyright Year	2005
Abstract	This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.
Starting Page	621
Ending Page	630
Page Count	10
File Format	PDF
ISSN	09238174
Journal	Journal of Electronic Testing
Volume Number	21
Issue Number	6
e-ISSN	15730727
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2005-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	timing specifications testing test environment yield analysis tester OTA and yield high-speed interconnect testing Computer-Aided Engineering (CAD, CAE) and Design Electronic and Computer Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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