NDLI: Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

Content Provider	Springer Nature Link
Author	Zalamea, Javier Llosa, Josep Ayguadé, Eduard Valero, Mateo
Copyright Year	2004
Abstract	High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. This paper reviews hardware and software techniques that alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be reduced if a high-capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation). Novel organizations for the register file based on clustering and hierarchical organization are necessary to meet the technology constraints. This paper proposes the used of a clustered organization and proposes an aggressive instruction scheduling technique that minimizes the negative effect of the limitations imposed by the register file organization.
Starting Page	447
Ending Page	474
Page Count	28
File Format	PDF
ISSN	08857458
Journal	International Journal of Parallel Programming
Volume Number	32
Issue Number	6
e-ISSN	15737640
Language	English
Publisher	Kluwer Academic Publishers-Plenum Publishers
Publisher Date	2004-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Software

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Power-Aware Compilation for Register File Energy Reduction

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

Achieving spilling-friendly register file assignment for highly distributed register files

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures

Experiences with Cooperating Register Allocation and Instruction Scheduling

Quantitative Evaluation of Register Pressure on Software Pipelined Loops

Register Saturation in Instruction Level Parallelism

Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions

Compiler Techniques for the Superthreaded Architectures$^{1, 2}$

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

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Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures

Achieving spilling-friendly register file assignment for highly distributed register files

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures

Experiences with Cooperating Register Allocation and Instruction Scheduling

Quantitative Evaluation of Register Pressure on Software Pipelined Loops

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