NDLI: Compilation Techniques for Multimedia Processors

Content Provider	Springer Nature Link
Author	Krall, Andreas Lelait, Sylvain
Copyright Year	2000
Abstract	The huge processing power needed by multimedia applications has led to multimedia extensions in the instruction set of microprocessors which exploit subword parallelism. Examples of these extended instruction sets are the Visual Instruction Set of the UltraSPARC processor, the AltiVec instruction set of the PowerPC processor, the MMX and ISS extensions of the Pentium processors, and the MAX-2 instruction set of the HP PA-RISC processor. Currently, these extensions can only be used by programs written in assembly language, through system libraries or by calling specialized macros in a high-level language. Therefore, these instructions are not used by most applications. We propose two code generation techniques to produce native code using these multimedia extensions for programs written in a high-level language: classical vectorization and vectorization by unrolling. Vectorization by unrolling is simpler than classical vectorization since data dependence analysis is reduced to acyclic control flow graph analysis. Furthermore, we address the problem of unaligned memory accesses. This can be handled by both static analysis and dynamic runtime checking. Preliminary experimental results for a code generator for the UltraSPARC VIS instruction set show that speedups of up to a factor of 4.8 are possible, and that vectorization by unrolling is much simpler but as effective as classical vectorization.
Starting Page	347
Ending Page	361
Page Count	15
File Format	PDF
ISSN	08857458
Journal	International Journal of Parallel Programming
Volume Number	28
Issue Number	4
e-ISSN	15737640
Language	English
Publisher	Kluwer Academic Publishers-Plenum Publishers
Publisher Date	2000-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Extended ANSI C for Processors with a Multimedia Extension

Compilation Techniques for High Level Parallel Code

Power-Aware Compilation for Register File Energy Reduction

A Vectorizing Compiler for Multimedia Extensions

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures

Special Issue On Embedded Processors – Guest Editor Introduction

Compiler Techniques for the Superthreaded Architectures$^{1, 2}$

Guest Editor Introduction: Special Issue on Embedded Processors

Region-based compilation: Introduction, motivation, and initial experience

Compilation Techniques for Multimedia Processors

Similar Documents

An Extended ANSI C for Processors with a Multimedia Extension

Compilation Techniques for High Level Parallel Code

Power-Aware Compilation for Register File Energy Reduction

A Vectorizing Compiler for Multimedia Extensions

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures

Special Issue On Embedded Processors – Guest Editor Introduction

Compiler Techniques for the Superthreaded Architectures$^{1, 2}$

Guest Editor Introduction: Special Issue on Embedded Processors

Region-based compilation: Introduction, motivation, and initial experience

Compilation Techniques for Multimedia Processors