NDLI: An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications

Content Provider	Springer Nature Link
Author	Iyer, Ravi Perdue, Jack Rauchwerger, Lawrence Amato, Nancy M. Bhuyan, Laxmi
Copyright Year	2005
Abstract	As processor technology continues to advance at a rapid pace, the principal performance bottleneck of shared memory systems has become the memory access latency. In order to understand the effects of cache and memory hierarchy on system latencies, performance analysts perform benchmark analysis on existing multiprocessors. In this study, we present a detailed comparison of two architectures, the HP V-Class and the SGI Origin 2000. Our goal is to compare and contrast design techniques used in these multiprocessors. We present the impact of processor design, cache/memory hierarchies and coherence protocol optimizations on the memory system performance of these multiprocessors. We also study the effect of parallelism overheads such as process creation and synchronization on the user-level performance of these multiprocessors. Our experimental methodology uses microbenchmarks as well as scientific applications to characterize the user-level performance. Our microbenchmark results show the impact of Ll/L2 cache size and TLB size on uniprocessor load/store latencies, the effect of coherence protocol design/optimizations and data sharing patterns on multiprocessor memory access latencies and finally the overhead of parallelism. Our application-based evaluation shows the impact of problem size, dominant sharing patterns and number of Processors used on speedup and raw execution time. Finally, we use hardware counter measurements to study the correlation of system-level performance metrics and the application’s execution time performance.
Starting Page	307
Ending Page	350
Page Count	44
File Format	PDF
ISSN	08857458
Journal	International Journal of Parallel Programming
Volume Number	33
Issue Number	4
e-ISSN	15737640
Language	English
Publisher	Kluwer Academic Publishers-Plenum Publishers
Publisher Date	2005-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Parallel architectures performance analysis shared memory Processor Architectures Software Engineering/Programming and Operating Systems Theory of Computation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

MulticoreBSP for C: A High-Performance Library for Shared-Memory Parallel Programming

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors$^{1}$

The Coming Wave of Multithreaded Chip Multiprocessors

Randomized parallel list ranking for distributed memory multiprocessors

Multi-Threaded Parallel I/O for OpenMP Applications

Exploiting Distributed-Memory and Shared-Memory Parallelism on Clusters of SMPs with Data Parallel Programs

A Scalable Farm Skeleton for Hybrid Parallel and Distributed Programming

Parallel Programming and Performance Evaluation with the URSA Tool Family

Combining Data and Computation Distribution Directives for Hybrid Parallel Programming : A Transformation System

An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications

Similar Documents

MulticoreBSP for C: A High-Performance Library for Shared-Memory Parallel Programming

An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors$^{1}$

The Coming Wave of Multithreaded Chip Multiprocessors

Randomized parallel list ranking for distributed memory multiprocessors

Multi-Threaded Parallel I/O for OpenMP Applications

Exploiting Distributed-Memory and Shared-Memory Parallelism on Clusters of SMPs with Data Parallel Programs

A Scalable Farm Skeleton for Hybrid Parallel and Distributed Programming

Parallel Programming and Performance Evaluation with the URSA Tool Family

Combining Data and Computation Distribution Directives for Hybrid Parallel Programming : A Transformation System

An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications