NDLI: Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications

Content Provider	Springer Nature Link
Author	Zhang, Chunhui Kurdahi, Fadi
Copyright Year	2007
Abstract	The iteration space of a loop nest is the set of all loop iterations bounded by the loop limits. Tiling the iteration space can effectively exploit the available parallelism, which is essential to multiprocessor compiling and pipelined architecture design. Another improvement brought by tiling is the better data locality that can dramatically reduce memory access and, consequently, the relevant memory access energy consumptions. However, previous studies on tiling were based on the data dependence, thus arrays without dependencies such as input arrays (data streams) were not considered. In this paper, we extend the tiling exploration to also accommodate those dependence-free arrays, and propose a stream-conscious tiling scheme for off-chip memory access optimization. We show that input arrays are as important, if not more, as the arrays with data dependencies when the focus is on memory access optimization instead of parallelism extraction. Our approach is verified on TI’s low power C55X DSP with popular multimedia applications, exhibiting off-chip memory access reduction by 67% on average over the traditional iteration space tiling.
Starting Page	63
Ending Page	98
Page Count	36
File Format	PDF
ISSN	08857458
Journal	International Journal of Parallel Programming
Volume Number	35
Issue Number	1
e-ISSN	15737640
Language	English
Publisher	Kluwer Academic Publishers-Plenum Publishers
Publisher Date	2007-02-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	tiling memory hierarchy data locality iteration space DSP low power Software Engineering/Programming and Operating Systems Processor Architectures Theory of Computation
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Information Systems Software

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Reuse-Driven Tiling for Improving Data Locality

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Improving Memory Hierarchy Performance for Irregular Applications Using Data and Computation Reorderings

Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory

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Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications

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