NDLI: Hardware implementation methods in Random Vector Functional-Link Networks

Content Provider	Springer Nature Link
Author	Martínez Villena, José M. Rosado Muñoz, Alfredo Soria Olivas, Emilio
Copyright Year	2014
Abstract	Recently appeared a renewed interest for Single Layer Feedforward Neural Network (SLF-NN) models where the hidden layer coefficients are randomly assigned and the output coefficients are calculated by a least square algorithm. In addition to random coefficient initialization, the main advantages for these learning models are the speed of training (no multiple iterations required) and no initial coefficient definition (e.g. no adaptation constant as in multilayer perceptron). These features are adequate for real time operation since a fast online training can be achieved, benefiting to applications (industrial, automotive, portable systems) where other neural networks learning approaches could not be used due to large resource usage, low speed and lack of flexibility. Thus, targeting hardware implementation allows its use in embedded systems, expanding its application areas to real time systems and, in general, those applications where the use of desktop computers is not possible. Typically, RVFLN demands a wide number of resources and a high computational burden; high dimension matrices are involved, and computation intensive algorithms are required to obtain the output layer coefficient values for the neural network, especially matrix inversion. This work describes the algorithm implementation and optimization of these models to fit embedded hardware system requirements together with a parameterizable model, allowing different applications to benefit from it. The proposal includes the use of fuzzy activation functions in neurons to reduce computations. An exhaustive analysis of three proposed different computation architectures for the learning algorithm is done. Classification results for three standard datasets and fixed point arithmetic are compared to Matlab floating point results, together with hardware related analysis as speed of operation, bit-length accuracy in fixed point arithmetic and logic resource occupation.
Starting Page	184
Ending Page	195
Page Count	12
File Format	PDF
ISSN	0924669X
Journal	Applied Intelligence
Volume Number	41
Issue Number	1
e-ISSN	15737497
Language	English
Publisher	Springer US
Publisher Date	2014-02-14
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Random Vector Functional-Link Networks Fast learning Matrix inversion Neural network training VHDL Embedded and real-time systems Artificial Intelligence (incl. Robotics) Mechanical Engineering Manufacturing, Machines, Tools
Content Type	Text
Resource Type	Article
Subject	Artificial Intelligence

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An Efficient Hardware Implementation of Feed-Forward Neural Networks

Fast Learning Algorithms for Feedforward Neural Networks

SR-30 turbojet engine real-time sensor health monitoring using neural networks, and Bayesian belief networks

FERNN: An Algorithm for Fast Extraction of Rules from Neural Networks

Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems

Training feedforward neural networks using multi-verse optimizer for binary classification problems

Neural Networks Approach to the Random Walk Dilemma of Financial Time Series

Network link prediction based on direct optimization of area under curve

Fuzzy Neural Network Models for Classification

Hardware implementation methods in Random Vector Functional-Link Networks

Similar Documents

An Efficient Hardware Implementation of Feed-Forward Neural Networks

Fast Learning Algorithms for Feedforward Neural Networks

SR-30 turbojet engine real-time sensor health monitoring using neural networks, and Bayesian belief networks

FERNN: An Algorithm for Fast Extraction of Rules from Neural Networks

Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems

Training feedforward neural networks using multi-verse optimizer for binary classification problems

Neural Networks Approach to the Random Walk Dilemma of Financial Time Series

Network link prediction based on direct optimization of area under curve

Fuzzy Neural Network Models for Classification

Hardware implementation methods in Random Vector Functional-Link Networks