NDLI: A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Content Provider	Springer Nature Link
Author	Chan, Michael J. Postula, Adam Ding, Yong Jozwiak, Lech
Copyright Year	2006
Abstract	Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving jitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.
Starting Page	131
Ending Page	140
Page Count	10
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	49
Issue Number	2
e-ISSN	15731979
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2006-06-27
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Bang-bang PLL Binary PLL Gain control Capture range Jitter Circuits and Systems Electronic and Computer Engineering Signal, Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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