NDLI: Inductance Modeling for On-Chip Interconnects

Content Provider	Springer Nature Link
Author	Tu, Shang Wei Shen, Wen Zen Chang, Yao Wen Chen, Tai Chen Jou, Jing Yang
Copyright Year	2003
Abstract	As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.
Starting Page	65
Ending Page	78
Page Count	14
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	35
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2003-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Electronic and Computer Engineering Signal, Image and Speech Processing Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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