NDLI: Noise in CMOS Voltage Controlled Relaxation Oscillators

Content Provider	Springer Nature Link
Author	Moore, Bruce
Copyright Year	2000
Abstract	A low-noise voltage controlled relaxation oscillator (VCO) has been fabricated in a 2 micron CMOS process. The VCO uses a grounded external timing capacitor and a bypassed latch. A theoretical analysis is presented showing that the VCOs output phase noise is dominated by the undersampling of circuit noise arising principally from the comparators. A minor correction to equation (21) of Abidi and Meyer in [1] is also derived. The VCO design was modified to allow a comparison between two different comparator architectures whilst sharing a common VCO core of current sources, timing capacitor and latch. Spectrum analyzer measurements are presented which confirm the theoretical predictions and show that high frequency signals are aliassed down to appear as noise sidebands about the carrier frequency. The oscillator's phase noise was measured as −70 dBc/Hz at a 20 kHz offset when oscillating at 1.1 MHz.
Starting Page	7
Ending Page	16
Page Count	10
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	23
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Kluwer Academic Publishers
Publisher Date	2000-01-01
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Electronic and Computer Engineering Signal, Image and Speech Processing Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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