NDLI: A 5th-order ΣΔ modulator with combination of op-Amp and CBSC circuit for ADSL applications

Content Provider	Springer Nature Link
Author	Zamani, M. Taghizadeh, M. Moghadasi, M. Naser Virdee, B. S.
Copyright Year	2011
Abstract	In this letter, a 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e−3.
Starting Page	143
Ending Page	150
Page Count	8
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	71
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2011-09-03
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Analog-to-digital data converter (ADC) Sigma delta modulator Comparator-based switched-capacitor circuit ADSL Signal, Image and Speech Processing Electrical Engineering Circuits and Systems
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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