NDLI: Improving HRR in 3P–8P harmonic rejection mixer using modified input transconductance stage in hard switching mixer

Content Provider	Springer Nature Link
Author	Ponnambalam, Maran Kanaga, Mythily Chandramani, Premanand Venkatesh
Copyright Year	2017
Abstract	This Paper focuses on improving the Harmonic Rejection Ratio (HRR) and the linearity of 3-Path 8-Phase harmonic rejection mixer with modified transconductance stage. The mixer core incorporates a feed-forward compensation technique in the transconductance stage for improving the linearity of the mixer with an Third order Input Intercept Point (IIP3) of 14 dBm. The Harmonic Rejection Mixer (HRM) using mixer cores with modified transconductance stage was designed using 90 nm CMOS process technology and the simulation results shows an improvement of IIP3 point of more than 25 dBm. A conversion gain of 12–4 dB was observed over the frequency range of 2.26–2.8 GHz (540 MHz bandwidth). Maximum third order HRR ( $$HRR_3$$ ) of 45 dB and fifth order HRR ( $$HRR_5$$ ) of 55 dB was observed on sweeping the RF power from −30 to 10 dBm. Deviations on the performance of the HRM was found to be very minimal on PVT variation.
Starting Page	1
Ending Page	7
Page Count	7
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	91
Issue Number	1
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2017-02-15
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Mixer Pseudosine LO (Local Oscillator) Harmonic rejection mixer (HRM) Linearity Harmonic rejection ratio (HRR) Circuits and Systems Electrical Engineering Signal,Image and Speech Processing
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

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