NDLI: Power consumption benchmarking for reconfigurable platforms

Content Provider	Springer Nature Link
Author	Pitkänen, Teemu Jamieson, Peter Becker, Tobias Moisio, Sami Takala, Jarmo
Copyright Year	2012
Abstract	Software defined radios (SDR) wideband mobile terminals must be capable of data processing while consuming low power and keeping the design and manufacturing costs as low as possible. SDR can combine high performance signal processing and flexibility, but power efficiency of SDR nodes is an issue that needs to be addressed. Analysis of power consumption for various target technologies is challenging, since each technology typically contains its own benchmarking tools and thus, results are not comparable. In this paper, we illustrate how the GroundHog2009 benchmark suite, designed to be platform independent, can be used to evaluate power dissipation of four modern FPGAs and one microcontroller. We also introduce a generic RTL library for the GroundHog2009 design cases and test bench infra-structure to make the toolset usage easy. In addition, we show that power can be saved by using clock management, available on one of the FGPA-boards. The power savings range from 38 to 1,150 %.
Starting Page	649
Ending Page	659
Page Count	11
File Format	PDF
ISSN	09251030
Journal	Analog Integrated Circuits and Signal Processing
Volume Number	73
Issue Number	2
e-ISSN	15731979
Language	English
Publisher	Springer US
Publisher Date	2012-09-08
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Power consumption GroundHog2009 FPGA Benchmark Signal, Image and Speech Processing Circuits and Systems Electrical Engineering
Content Type	Text
Resource Type	Article
Subject	Surfaces, Coatings and Films Signal Processing Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA implementation of high-speed neural network for power amplifier behavioral modeling

FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling

An efficient parallel architecture for ray-tracing

Parasitic compensation in CCI-based circuits for reduced power consumption

A Low-Power Reconfigurable Analog Filter for UMTS/WLAN Receivers

Power consumption of analog circuits: a tutorial

Power harvesting with PZT ceramics and circuits design

FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver

A software-defined radio FPGA implementation of OFDM-based PHY transceiver for 5G

Power consumption benchmarking for reconfigurable platforms

Similar Documents

FPGA implementation of high-speed neural network for power amplifier behavioral modeling

FPGA-implementation of dynamic time delay neural network for power amplifier behavioral modeling

An efficient parallel architecture for ray-tracing

Parasitic compensation in CCI-based circuits for reduced power consumption

A Low-Power Reconfigurable Analog Filter for UMTS/WLAN Receivers

Power consumption of analog circuits: a tutorial

Power harvesting with PZT ceramics and circuits design

FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver

A software-defined radio FPGA implementation of OFDM-based PHY transceiver for 5G

Power consumption benchmarking for reconfigurable platforms