NDLI: Efficient inter-core power and thermal balancing for multicore processors

Please wait, while we are loading the content...

Efficient inter-core power and thermal balancing for multicore processors

Content Provider	Springer Nature Link
Author	Cebrián, Juan M. Sánchez, Daniel Aragón, Juan L. Kaxiras, Stefas
Copyright Year	2012
Abstract	Nowadays the market is dominated by processor architectures that employ multiple cores per chip. These architectures have different behavior depending on the applications running on the processor (parallel, multiprogrammed, sequential), but all happen to meet what is called the power and temperature wall. For future technologies (less than 22 nm) and a fixed die size, it is still uncertain the percentage of processor that can be simultaneously powered on. Power saving and power budget mechanisms can be useful to precisely control the amount of power been dissipated by the processor. After an initial analysis we discover that legacy power saving techniques work properly for matching a power budget in thread-independent and multi-programmed workloads, but not in parallel workloads. When running parallel shared-memory applications sacrificing some performance in a single core (thread) in order to be more energy-efficient can unintentionally delay the rest of cores (threads) due to synchronization points (locks/barriers), having a negative impact on global performance. In order to solve this problem we propose power token balancing (PTB) aimed at accurately matching an external power constraint by balancing the power consumed among the different cores. Experimental results show that PTB matches more accurately a predefined power budget (50 % of the original peak power) than other mechanisms like DVFS. The total energy consumed over the budget is reduced to only 8 % for a 16-core CMP with only a 3 % energy increase (overhead). We also introduce a novel mechanism named “Nitro”. Nitro will overclock the core that enters a critical section (delimited by locks) in order to free the lock as soon as possible. Experimental results have shown that Nitro is able to reduce the execution time of lock-intensive applications in more than 4 % by overclocking the frequency by 15 % in selected program phases over a period of time that represents a 22 % of the total execution time. We conclude the work with an analysis of the thermal effects of PTB in different CMP configurations using realistic power numbers and heatsink/fan configurations. Results show how PTB not only balances temperature between the different cores, reducing temperature gradient and increasing signal reliability, but also allows a reduction of 28–30 % of both average and peak temperatures for the studied benchmarks when a peak power budget of 50 % is exceeded.
Starting Page	537
Ending Page	566
Page Count	30
File Format	PDF
ISSN	0010485X
Journal	Computing
Volume Number	95
Issue Number	7
e-ISSN	14365057
Language	English
Publisher	Springer Vienna
Publisher Date	2012-11-15
Publisher Place	Vienna
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Power consumption Power budget Power tokens Chip multiprocessor Computer Science Information Systems Applications (incl. Internet) Computer Communication Networks Software Engineering Artificial Intelligence (incl. Robotics) Computer Application in Administrative Data Processing
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Computational Mathematics Numerical Analysis Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Internet visualization

Special issue on on-chip parallel and network-based systems

A survey and taxonomy on energy efficient resource allocation techniques for cloud computing systems

Introduction to the computing special issue: performance portability and tuning for multi-core and many-core computing systems

Efficent and highly portable deterministic multithreading (DetLock)

Sustainable mobile computing

From Methods to Images

Energy-centric DVFS controlling method for multi-core platforms

Energy Efficient Block-Partitioned Multicore Processors for Parallel Applications

Efficient inter-core power and thermal balancing for multicore processors

Similar Documents

Internet visualization

Special issue on on-chip parallel and network-based systems

A survey and taxonomy on energy efficient resource allocation techniques for cloud computing systems

Introduction to the computing special issue: performance portability and tuning for multi-core and many-core computing systems

Efficent and highly portable deterministic multithreading (DetLock)

Sustainable mobile computing

From Methods to Images

Energy-centric DVFS controlling method for multi-core platforms

Energy Efficient Block-Partitioned Multicore Processors for Parallel Applications

Efficient inter-core power and thermal balancing for multicore processors