NDLI: A novel CMOS process compatible high performance parallel-stacked RF spiral inductor

Content Provider	Springer Nature Link
Author	Jair, D. K. Hsieh, Ming Chun Lin, C. S.
Copyright Year	2009
Abstract	In this study, a deep-submicron CMOS process compatible parallel-stacked inductor has been successfully developed. We use the mature CMOS compatible technology and air gap structure to reduce substrate losses and parallel-stacked structure to reduce the resistance, thus can promote the Q factor. Experimental results evidence that by using the parallel-stacked structure, the chip area can be reduced significantly for the issue of continuing reduction of the chip size. Furthermore, the resistance can be reduced by using the parallel-stacked structure and thus results in an obviously improving of the Q at low frequency. The measured peak Q and peak-Q frequency with the parallel metal layer of M8//M7//M6//M5 are 7.06 and 1.8 GHz, thus enhancing its applications for higher frequency RF IC. Therefore, the developed deep-submicron CMOS process compatible parallel-stacked inductor is suitable for CMOS RF integrated circuit applications.
Starting Page	1175
Ending Page	1179
Page Count	5
File Format	PDF
ISSN	09467076
Journal	Microsystem Technologies
Volume Number	16
Issue Number	7
e-ISSN	14321858
Language	English
Publisher	Springer-Verlag
Publisher Date	2009-12-15
Publisher Place	Berlin, Heidelberg
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Electronics and Microelectronics, Instrumentation Mechanical Engineering Nanotechnology
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering Hardware and Architecture

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