NDLI: New algorithms for minimizing the longest wire length during circuit compaction

Content Provider	Springer Nature Link
Author	Hambrusch, S. E. Tu, Hung Yi
Copyright Year	1997
Abstract	Consider the problem of performing one-dimensional circuit compaction for a layout containingn h horizontal wires andn layout cells. We present new and efficient constrain-graph-based algorithms for generating a compacted layout in which either the length of the longest wires or a user-specified tradeoff function between the layout width and the longest wire length is minimized. Both algorithms have anO(n h ·nlogn) running time. The concept employed by our algorithms is that of assigning speeds to the layout cells. Speeds are computed by performing path computations in subgraphs of the constraint graphs. A compacted layout is generated over a number of iterations, with each iteration first determining speeds and then moving the layout elements to the right according to the computed speeds. Each iteration produces a better layout and after at mostn·n h iterations the final layout is produced.
Starting Page	426
Ending Page	448
Page Count	23
File Format	PDF
ISSN	01784617
Journal	Algorithmica
Volume Number	17
Issue Number	4
e-ISSN	14320541
Language	English
Publisher	Springer-Verlag
Publisher Date	1997-01-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Analysis of algorithms Circuit layout Compaction Layout width Longest wire length Path computations Computer Systems Organization and Communication Networks Data Structures, Cryptology and Information Theory Theory of Computation Algorithm Analysis and Problem Complexity Mathematics of Computing Algorithms
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Computer Science Applications

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