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| Content Provider | Springer Nature Link |
|---|---|
| Author | Kwles, Pyarelal Leach, Geoff Zambetta, Fabio |
| Copyright Year | 2014 |
| Abstract | Exact order-independent transparency (OIT) techniques capture all fragments during rasterization. The fragments are then sorted per-pixel by depth and composited in order using alpha transparency. The sorting stage is a bottleneck for high depth complexity scenes, taking 70–95 % of the total time for those investigated. In this paper, we show that typical shader-based sorting speed is impacted by local memory latency and occupancy. We present and discuss the use of both registers and an external merge sort in register-based block sort to better use the memory hierarchy of the GPU for improved OIT rendering performance. This approach builds upon backwards memory allocation, achieving an OIT rendering speed up to 1.7 $$\times $$ that of the best previous method and 6.3 $$\times $$ that of the common straight forward OIT implementation. In some cases, the sorting stage is reduced to no longer be the dominant OIT component. |
| Starting Page | 603 |
| Ending Page | 613 |
| Page Count | 11 |
| File Format | |
| ISSN | 01782789 |
| Journal | The Visual Computer |
| Volume Number | 30 |
| Issue Number | 6-8 |
| e-ISSN | 14322315 |
| Language | English |
| Publisher | Springer Berlin Heidelberg |
| Publisher Date | 2014-05-28 |
| Publisher Place | Berlin, Heidelberg |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Sorting OIT Transparency Shaders Performance Registers Register-based block sort Computer Graphics Computer Science Artificial Intelligence (incl. Robotics) Image Processing and Computer Vision |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Vision and Pattern Recognition Software |
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