NDLI: An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Content Provider	Springer Nature Link
Author	Moghaddam, Majid Timarchi, Somayeh Moaiyeri, Mohammad Hossein Eshghi, Mohammad
Copyright Year	2015
Abstract	This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body–source voltage dynamically. Proper usage of low-threshold voltage (L- $$V_{\mathrm{t}}$$ ) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature.
Starting Page	1437
Ending Page	1455
Page Count	19
File Format	PDF
ISSN	0278081X
Journal	Circuits, Systems, and Signal Processing
Volume Number	35
Issue Number	5
e-ISSN	15315878
Language	English
Publisher	Springer US
Publisher Date	2015-07-24
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	SRAM Low voltage Low power Threshold voltage techniques Leakage current PVT variations Circuits and Systems Electrical Engineering Signal, Image and Speech Processing Electronics and Microelectronics, Instrumentation
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Signal Processing

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

A Novel Ultra-Low-Power Low-Voltage Femto-Ampère Current Mirror

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

Ultra Low Power Improved Differential Amplifier

Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits

Low-Voltage Current Feedback Operational Amplifiers

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

A Low Voltage and Low Power Current-Mode Analog Computational Circuit

Differential Difference Current Conveyor Using Bulk-Driven Technique for Ultra-Low-Voltage Applications

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Similar Documents

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

A Novel Ultra-Low-Power Low-Voltage Femto-Ampère Current Mirror

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

Ultra Low Power Improved Differential Amplifier

Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits

Low-Voltage Current Feedback Operational Amplifiers

A Novel Resistor-Free Electronically Adjustable Current-Mode Instrumentation Amplifier

A Low Voltage and Low Power Current-Mode Analog Computational Circuit

Differential Difference Current Conveyor Using Bulk-Driven Technique for Ultra-Low-Voltage Applications

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques