NDLI: Efficient Implementations for AES Encryption and Decryption

Content Provider	Springer Nature Link
Author	Rachh, Rashmi Ramesh Mohan, P. V. Ananda Anami, B. S.
Copyright Year	2012
Abstract	This paper proposes two efficient architectures for hardware implementation of the Advanced Encryption Standard (AES) algorithm. The composite field arithmetic for implementing SubBytes (S-box) and InvSubBytes (Inverse S-box) transformations investigated by several authors is used as the basis for deriving the proposed architectures. The first architecture for encryption is based on optimized S-box followed by bit-wise implementation of MixColumns and AddRoundKey and optimized Inverse S-box followed by bit-wise implementation of InvMixColumns and AddMixRoundKey for decryption. The proposed S-box and Inverse S-box used in this architecture are designed as a cascade of three blocks. In the second proposed architecture, the block III of the proposed S-box is combined with the MixColumns and AddRoundKey transformations forming an integrated unit for encryption. An integrated unit for decryption combining the block III of the proposed InvSubBytes with InvMixColumns and AddMixRoundKey is formed on similar lines. The delays of the proposed architectures for VLSI implementation are found to be the shortest compared to the state-of-the-art implementations of AES operating in non-feedback mode. Iterative and fully unrolled sub-pipelined designs including key schedule are implemented using FPGA and ASIC. The proposed designs are efficient in terms of Kgates/Giga-bits per second ratio compared with few recent state-of-the-art ASIC (0.18-μm CMOS standard cell) based designs and throughput per area (TPA) for FPGA implementations.
Starting Page	1765
Ending Page	1785
Page Count	21
File Format	PDF
ISSN	0278081X
Journal	Circuits, Systems, and Signal Processing
Volume Number	31
Issue Number	5
e-ISSN	15315878
Language	English
Publisher	SP Birkhäuser Verlag Boston
Publisher Date	2012-03-03
Publisher Place	Boston
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Advanced Encryption Standard Encryption Decryption FPGA implementation VLSI architectures Signal, Image and Speech Processing Circuits and Systems Electrical Engineering Electronics and Microelectronics, Instrumentation
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Signal Processing

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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