NDLI: Dual-Issue Scheduling for Binary Trees with Spills and Pipelined Loads

Content Provider	Society for Industrial and Applied Mathematics (SIAM)
Author	Meleis, Waleed M.
Copyright Year	2001
Abstract	We describe an algorithm that finds a minimum cost schedule, including spill code, for a register-constrained machine that can issue up to one arithmetic operation and one memory access operation at a time, under the restrictions that the dependence graph is a full binary tree, all arithmetic and store operations have unit latency, and all load operations have a latency of 1 or all load operations have a latency of 2. This problem is a generalization of two problems whose efficient solutions are well understood: optimaldual-issue scheduling without spills for binary expression trees, solved by Bernstein, Jaffe, and Rodeh [SIAM J. Comput., 18 (1989), pp. 1098--1127], and optimal single-issue scheduling with spill code and delayed loads, solved by Kurlander, Proebsting, and Fischer [ ACM Transactions on Programming Languages and Systems, 17 (1995), pp. 740--776], both assuming a fixed number of registers. We show that the algorithm's complexity is O(nk) where n is the number of operations to be scheduled and k is the number of spills in the schedule. The cost of a "contiguous" schedule (i.e., its length) is shown to be $\rho + 2k + g + \|A\|$, where $\rho$ is the number of registers used, \|A\| is the number of arithmetic operations, k is the number of spills, and g is the number of empty slots in the associated single processor schedule. Therefore all contiguous schedules formed from optimal single processor schedules have minimum cost.
Starting Page	1921
Ending Page	1941
Page Count	21
File Format	PDF
ISSN	00975397
DOI	10.1137/S009753979834610X
e-ISSN	10957111
Journal	SIAM Journal on Computing (SMJCAT)
Issue Number	6
Volume Number	30
Language	English
Publisher	Society for Industrial and Applied Mathematics
Publisher Date	2006-07-27
Access Restriction	Subscribed
Subject Keyword	scheduling algorithms code generations registers Compilers and interpreters Scheduling theory, deterministic Combinatorics parallel functional units
Content Type	Text
Resource Type	Article
Subject	Mathematics Computer Science

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