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New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
| Content Provider | Semantic Scholar |
|---|---|
| Author | Ker, Ming-Dou Chenb, T.-Y. Changb, H.-H. |
| Copyright Year | 1999 |
| Abstract | New layout design to eectively reduce the layout area of CMOS output transistors but with higher driving capability and better ESD reliability is proposed. The output transistors of large device dimensions are assembled by a plurality of the basic layout cells, which have the square, hexagonal or octagonal shapes. The output transistors realized by these new layout styles have more symmetrical device structures, which can be more uniformly triggered during the ESD-stress events. With theoretical calculation and experimental veri®cation, both higher output driving/ sinking current and stronger ESD robustness of CMOS output buers can be practically achieved by the proposed new layout styles within a smaller layout area in the non-silicided bulk CMOS process. The output transistors assembled by a plurality of the proposed layout cells also have a lower gate resistance and a smaller drain capacitance than that realized by the traditional ®nger-type layout. # 1999 Elsevier Science Ltd. All rights reserved. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ics.ee.nctu.edu.tw/~mdker/Referred%20Journal%20Papers/New_layout_JMR_99.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | CMOS Cations Dimensions ESD gene Electric Capacitance Esd protein, rat Fetal blood:Vol:Pt:Bld:Qn Primula veris Silicon Small Spectral density Transistor |
| Content Type | Text |
| Resource Type | Article |
