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Neural Hierarchical Sequence Model for Irregular Data Prefetching
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shi, Zhan |
| Copyright Year | 2019 |
| Abstract | Data prefetchers are common hardware structures that improve processor performance by hiding the long latency of DRAM memory accesses. In particular, data prefetchers predict the memory addresses of data that the program will access in the near future. From a machine learning perspective, the challenge is to accurately predict memory accesses that span across a huge address space. To address this challenge, this paper introduces a neural hierarchical sequence model that can accommodate the vast input space and that makes pure data addresses a viable feature for neural networks. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.cs.utexas.edu/users/lin/papers/mlsys19.pdf |
| Alternate Webpage(s) | https://www.cs.utexas.edu/~akanksha/neural_hierarchical_shi_2019.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
