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Arquitecturas de complejidad reducida para la compensación electrónica de la dispersión en sistemas de comunicaciones de alta velocidad
| Content Provider | Semantic Scholar |
|---|---|
| Author | Pola, Ariel L. |
| Copyright Year | 2016 |
| Abstract | As a result of the steady increase in data traffic, the telecommunications industry has evolved dramatically in recent years. In this context, new digital communications transceivers that outperform processing speed are required. This speed increase combined with the limitations of the bandwidth communications channel exacerbate the impacts of the intersymbol interference (ISI). In order to compensate for this effect, it is necessary to implement efficient receiver equalization schemes. The decision feedback equalizer (DFE) is one of the most popular equalization techniques in industry, featuring a good relationship between performance and complexity. Unfortunately, its use in high speed systems has been limited due to the high complexity reached when processing techniques are used in parallel as a result of the existence of feedback loops. In particular, the complexity of the existing techniques increases exponentially with the channel memory, leading to a restriction in the use of such equalizers for moderate ISI. This Thesis proposes a new scheme of reduced complexity iterative equalization for high-speed receivers. The new Decision FeedForward Equalizer (DFFE) allows for a similar performance to the DFE but with a parallelizable architecture whose complexity increases quadratically with the channel memory. For channels with large ISI, this results in a drastic reduction in complexity compared to the DFE. The main feature of the DFFE is the iteration of tentative decisions to improve the accuracy of the ISI estimation. With the purpose of investigating the performance of the new receiver, a theoretical study is developed and the DFFE is verified by extensive computer simulations. The second contribution of the present Thesis is a detailed analysis of processing complexity and the implementation in FPGA of parallel DFFE. This study allows to demonstrate the important benefits of using a forward implementation architecture and verify experimentally the performance of DFFE. All these advantages make the DFFE an excellent choice for system receivers of digital high-speed communications. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://repositoriodigital.uns.edu.ar/bitstream/123456789/2993/1/20160909_TesisPhD_ArielPola.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
