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Modeling Snapback and Rise-time Effects in TLP Testing for ESD MOS Devices using BSIM3 and VBIC Models
| Content Provider | Semantic Scholar |
|---|---|
| Author | Carroll, Richard Connerney, D. Luk, Timwah Zhou, Yun-Song |
| Copyright Year | 2005 |
| Abstract | A simple SPICE macro model has been created for ESD MOS modeling. The model consists of standard components only, mainly a MOS transistor modeled by BSIM3v3, a bipolar transistor modeled by VBIC, and a resistor for substrate resistance. It offers advantages of convenience in CAD implementation, high simulation speed, wider availability, and less convergence issues. The modeling approach has been used to investigate rise-time effects in TLP stress testing. The simulation, as well as measurement, demonstrated that the rising edge of TLP pulse affects snapback trigger voltage Vt1 not only in gate coupled NMOS but also grounded gate NMOS devices. It implies that the base transit time and the junction capacitance of parasitic BJT have impact on trigger voltage Vt1. |
| Starting Page | 199 |
| Ending Page | 202 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.nsti.org/Nanotech2005/WCM2005/WCM2005-YZhou.pdf |
| Alternate Webpage(s) | http://www.nsti.org/publications/Nanotech/2005/pdf/827.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
