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Vliw processors: efficiently exploiting instruction level parallelism
| Content Provider | Semantic Scholar |
|---|---|
| Author | Flynn, Michael J. Rudd, Kevin W. |
| Copyright Year | 2000 |
| Abstract | This dissertation explores high-performance complexity-efficient processors foc u ing on VLIW processors. Complexity efficiency is a qualitative characteristi c that describes a system where performance has not reached the point of diminishing returns. Using the techniques described in this dissertation, simple statically-scheduled ve ry-long-instructionword (VLIW) processors can be efficient architectures for exploiting instruc tion-level parallelism and can effectively address the needs of general purpose computing. We studied the ability of dynamic execution to exploit instruction-level parall elism in dynamic VLIW processors. Unlike previous studies, this study explores the benefits of dynamic execution on an instruction stream with explicit instruction-level parallelism. Dynamic execution is thus applied to problems that compilers have difficulty solving rather than to those problems that compilers readily solve reducing the need for complex a nd costly hardware. In addition to presenting performance results, we also des cribe a general processor model and execution definition that improves upon the precise execution m odel used in traditional processors; we also describe the simulator that impleme nts this new execution model. In our simulations we varied a number of parameters allowing ext raction of the individual effects of each parameter on performance. These simulation r esults show that although a small amount of reordering is adequate to eliminate almost all pena lties associated with scheduling errors and latency variations, even a signific ant amount of reordering is inadequate to eliminate the penalty associated with branch mispr edictions and long memory latencies. As an alternative to dynamic VLIW processors, we developed Replay Buffers to xtend static VLIW processors to support efficient multi-threading. Replay Buffers provide zero switch-cycle thread switches as well as overhead-free exception handling (beyond the cost |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://umunhum.stanford.edu/~kevin/pubs/991203-final-dissertation-ds.ps.gz |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
