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A Reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b Low-Power 0.13um CMOS Pipeline ADC
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2009 |
| Abstract | This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b low-power 0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC capacitor mismatch while the flash ADCs employ a switched-bias power-reduction technique to reduce the power consumption of comparators. The CMOS on-chip I/V references operate at a supply ranging from 0.5V to 1.2V with optional off-chip voltage references. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB, respectively. The ADC with an active die area of 0.98mm shows the maximum SNDR and SFDR of 52dB and 65dB, respectively, and a power consumption of 22.4mW at a typical condition, 0.8V and 70MS/s. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://eeic7.sogang.ac.kr/paper%20file/domestic%20conference/%5B42%5D_13th_Samsung_10b70mADC.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
