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A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio
| Content Provider | Semantic Scholar |
|---|---|
| Author | Gramegna, Giuseppe Mattos, P. G. Losi, Marco Das, Sauparna Franciotta, Massimo Bellantone, N. G. Vaiana, Michele Mandara, Valentina Paparo, Mario |
| Copyright Year | 2006 |
| Abstract | A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption. |
| Starting Page | 540 |
| Ending Page | 551 |
| Page Count | 12 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/JSSC.2005.864136 |
| Volume Number | 41 |
| Alternate Webpage(s) | https://www.brown.edu/Departments/Engineering/Courses/En162/GramengaArticleGPS.pdf |
| Alternate Webpage(s) | http://www.brown.edu/Departments/Engineering/Courses/En162/GramengaArticleGPS.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/JSSC.2005.864136 |
| Journal | IEEE Journal of Solid-State Circuits |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
