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A Framework for Scalable Post-Silicon Statistical Delay Prediction under Spatial Variations
| Content Provider | Semantic Scholar |
|---|---|
| Author | Liu, Qunzeng Sapatnekar, Sachin S. |
| Copyright Year | 2009 |
| Abstract | Due to increased variability trends in nanoscale integrated circuits, statistical circuit analysis and optimization has become essential. While statistical timing analysis ha s an important role to play in this process, it is equally important to develop die-specific delay prediction techniques using p ostsilicon measurements. We present a novel method for postsilicon delay analysis. We gather data from a small number of on-chip test structures, and combine this information wi th presilicon statistical timing analysis to obtain narrow, die-specific, timing probability density function (PDF). Experimental r esults show that for the benchmark suite being considered, taking a ll parameter variations into consideration, our approach canobtain a PDF whose standard deviation is 79.0% smaller, on average, than the statistical timing analysis result. The accuracy of the method defined by our metric is 99.6% compared to Monte-Carlo simulation. The approach is scalable to smaller test struct ure overheads and can still produce acceptable results. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.umn.edu/users/sachin/jnl/tcad09ql.pdf |
| Alternate Webpage(s) | http://www.ee.umn.edu/users/sachin/jnl/tcad09ql.pdf |
| Alternate Webpage(s) | http://www.ece.umn.edu/~sachin/jnl/tcad09ql.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
