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Design Of High Performance Reconfigurable Routers Using Fpga
| Content Provider | Semantic Scholar |
|---|---|
| Author | Parthasarathi, Rishikesh Karunakaran, Prasanth Venkatraman, Sitalakshmi Dineshkumar, Thanigachalam Shanavas, I. Hameem |
| Copyright Year | 2012 |
| Abstract | *Abstrsact — Network-on-chip(NoC) architectures are emerging for the highly scalable, reliable, and modular on-chip communication infrastructure platform. The NoC architecture uses layered protocols and packet-switched networks which consist of on-chip routers, links, and network interfaces on a predefined topology. In this Project, we design network-on-chip which is based on the Cartesian network environment. This project proposes the new Cartesian topology which is used to reduce network routing time, and it is a suitable alternate to network design and implementation. The Cartesian Network-OnChip can be modeled using Verilog HDL and simulated using Modelsim software. |
| Starting Page | 46 |
| Ending Page | 52 |
| Page Count | 7 |
| File Format | PDF HTM / HTML |
| DOI | 10.5815/ijieeb.2012.04.07 |
| Volume Number | 4 |
| Alternate Webpage(s) | http://www.mecs-press.org/ijieeb/ijieeb-v4-n4/IJIEEB-V4-N4-7.pdf |
| Alternate Webpage(s) | https://doi.org/10.5815/ijieeb.2012.04.07 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
