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Design of high-throughput SHA-256 hash function based on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Suhaili, Shamsiah Binti Watanabe, Takahiro |
| Copyright Year | 2017 |
| Abstract | Nowadays, security has become an important topic of interest to researchers. Different types of cryptography algorithms have been developed in order to improve the performance of these information-protecting procedures. A hash function is a cryptography algorithm without a key such as MD5, RIPEMD160, and SHA-1. In this paper, a new SHA family is developed and designed in order to fulfil the cryptographic algorithm performance requirement. Thus, SHA-256 design and SHA-256 unfolding design based on reconfigurable hardware have been successfully completed using Verilog code. These designs were simulated and verified using ModelSim. The results showed that the proposed SHA-256 unfolding design gave better performance on Arria II GX in terms of throughput. The high throughput of SHA-256 unfolding design was obtained at a data transfer speed of 2429.52 Mbps. |
| Starting Page | 1 |
| Ending Page | 6 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/ICEEI.2017.8312449 |
| Alternate Webpage(s) | https://ir.unimas.my/id/eprint/26218/1/Design%20of%20high-throughput%20SHA-256%20hash%20function%20based%20on%20FPGA%20(abstract).pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/ICEEI.2017.8312449 |
| Journal | 2017 6th International Conference on Electrical Engineering and Informatics (ICEEI) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
