NDLI: A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

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A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

Content Provider	Semantic Scholar
Author	Chiu, Yun Gray, P. Nikolić, Borivoje
Copyright Year	2004
Abstract	A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.
Starting Page	2139
Ending Page	2151
Page Count	13
File Format	PDF HTM / HTML
DOI	10.1109/JSSC.2004.836232
Volume Number	39
Alternate Webpage(s)	http://www.eecs.berkeley.edu/~bora/Journals/2004/JSSC-0412.pdf
Alternate Webpage(s)	http://infopad.eecs.berkeley.edu/Publications/2004/JOURNALS/Bora/JSSC-0412.pdf
Alternate Webpage(s)	http://www.eecs.berkeley.edu/~bora/publications/JSSC-0412.pdf
Alternate Webpage(s)	https://people.eecs.berkeley.edu/~bora/publications/JSSC-0412.pdf
Alternate Webpage(s)	http://people.eecs.berkeley.edu/~bora/publications/JSSC-0412.pdf
Alternate Webpage(s)	https://doi.org/10.1109/JSSC.2004.836232
Journal	IEEE Journal of Solid-State Circuits
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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