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Post silicon validation of analog/mixed signal/RF circuits and systems: recent advances
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chatterjee, Abhijit Deyati, Sabyasachi Muldrey, Barry John |
| Copyright Year | 2016 |
| Abstract | Technology scaling along with unprecedented levels of device integration has led to increasing numbers of analog/mixed-signal/RF design bugs escaping into silicon. Such bugs are manifested under specific system-on-chip (SoC) operating conditions and their effects are difficult to predict a-priori. This paper describes recent advances in detecting and diagnosing such bugs using "guided" stochastic test stimulus generation algorithms. A key challenge is that unlike traditional test generation for manufacturing test that is predicated on known failure mechanisms, the nature of design bugs is generally unknown and must be discovered on-the-fly. Classes of design errors from undesired capacitive coupling and incorrect biasing conditions to incorrect guard-banding of designs are considered. It is shown that high design bug coverage can be obtained over a range of test cases. |
| Starting Page | 1 |
| Ending Page | 6 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/IMS3TW.2016.7524222 |
| Alternate Webpage(s) | https://ia601506.us.archive.org/zipview.php?file=10.1109@ims3tw.2016.7524222.pdf&zip=/3/items/ieee-us-government-works-dir/ieee-us-government-works-dir.zip |
| Alternate Webpage(s) | https://doi.org/10.1109/IMS3TW.2016.7524222 |
| Journal | 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW) |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
