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Compiler Controlled Register Stack Management for the Intel R Itanium R Architecture
| Content Provider | Semantic Scholar |
|---|---|
| Author | Settle, Alex Connors, Daniel A. Lavery, Gerolf Hoflehner Dan |
| Copyright Year | 2004 |
| Abstract | Intel Itanium processors were designed with an on chip register stack engine (RSE) in order to reduce the overhead related to procedure call boundaries. The RSE automatically preserves values stored in stacked registers across procedure invocations. This architecture model significantly reduces the amount of spill code necessary to maintain an application’s state, which in turn reduces memory traffic. Despite the benefits provided by the RSE, CPU stalls due to register stack overflow and underflow can contribute significantly to the overall execution time of many applications. This paper presents a method for reducing these stalls by allowing the compiler to manage the size of the stacked register set assigned to a given procedure. The proposed compiler optimization was integrated into version 7.1 of the Intel Itanium compiler, and tested on the SpecCInt2000 benchmark suite. The results indicate that allowing the compiler to manage RSE usage produces a 10% drop in processor stall cycles related to RSE traffic. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ucdenver.edu/faculty-staff/dconnors/Documents/papers/epic04-regstack.pdf |
| Alternate Webpage(s) | http://rogue.colorado.edu/draco/papers/epic04-regstack.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
