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An 8b 250MS/s 0.13µm CMOS ADC using variable references for VGA-to-WUXGA scaler chips
| Content Provider | Semantic Scholar |
|---|---|
| Author | Park, Hye-Lim Myung, Sung-Meen Kim, Younglok Lee, Seung-Hoon |
| Copyright Year | 2012 |
| Abstract | This work proposes an 8b 250MS/s 0.13µm CMOS two-step pipeline ADC using variable references for VGA-to-WUXGA scaler chip applications. The input sample-and-hold amplifier employs MOS capacitor-based gate-bootstrapping circuits to keep the on-resistance of sampling switches constant and to sample wide-band wide-range variable inputs with least distortion. The capacitors of the proposed multiplying D/A converter are laid out in a high matching one-dimensional symmetric shape rather than the conventional common-centroid topology to save chip area. The proposed on-chip current and voltage reference circuits generate variable bottom-side reference voltages with a fixed top-side reference using a single external voltage for processing wide-range variable analog inputs. The two-step reference selection scheme reduces considerably power and area in the last-stage 5b flash ADC. The prototype ADC in a 0.13µm CMOS demonstrates measured differential and integral non-linearities within 0.35 and 0.54 LSB, respectively. The ADC shows a maximum SNDR and SFDR of 44.4 and 56.1 dB at 250 MS/s, respectively. The ADC with an active die area of 0.72 mm2 consumes 58.8–62.4 mW depending on input modes at 250 MS/s and 1.2 V. |
| Starting Page | 233 |
| Ending Page | 242 |
| Page Count | 10 |
| File Format | PDF HTM / HTML |
| DOI | 10.1007/s10470-012-9900-1 |
| Volume Number | 73 |
| Alternate Webpage(s) | http://eeic7.sogang.ac.kr/paper%20file/international%20journal/%5B48%5DAICSP12_ADC8b250MSs.pdf |
| Alternate Webpage(s) | https://doi.org/10.1007/s10470-012-9900-1 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
