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Computational Modeling of Negative Bias Temperature Instability ( NBTI ) for Reliability-aware VLSI Design
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kufluoglu, Haldun Paul, Bipul C. Kang, K. Alam, Muhammad Ashraful |
| Copyright Year | 2005 |
| Abstract | Modeling of temporal degradation in CMOS circuits due to NBTI and a design methodology to overcome its reliability limits are presented. Device-level NBTI is modeled and calibrated to experimental data. Implications of the model for future-generation devices mentioned in ITRS are discussed. The framework for performance degradation of circuits is established. The tools are then applied on benchmark circuits of different technology generations. Time-dependent parametric variations are obtained for the circuits and a straight-forward sizing algorithm is proposed. The results show that NBTI-reliable circuits can be achieved with small area overhead and this technique is effective for upcoming technology generations. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://engineering.purdue.edu/~alamgrp/papers-pdf/2005-Techcon-Kufluoglu-Computational_NBTI.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
