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Using ChipScope Pro to Debug Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE Designs for PCI Express
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wiltgen, Jake McGuirk, Michael A. Ayer, John D. |
| Copyright Year | 2007 |
| Abstract | ChipScope™ Pro can be used to detect and debug design problems not discovered during simulation in LogiCORE™ IP cores for PCI Express® (PCIe). This document provides information for debugging board level problems by using ChipScope Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices. There are two methods to insert ChipScope ICON and ILA cores into a design. The ChipScope ILA and ICON cores can be inserted into specific levels of Xilinx solutions for PCIe to track incoming and outgoing Transaction Layer Packets (TLP), as received and generated by the user logic. This application note contains instructions for inserting ChipScope ILA and ICON cores into the PCIe cores to capture TLP and Data Link Layer Packet (DLLP) link traffic; thus providing insight to the bus operation and visibility into packet handling within the core. This is especially useful if a link analyzer for PCIe is not available to debug the link. This application note also discusses two methods of inserting the ChipScope Pro ICON and ILA cores into Endpoint for PCIe cores. The first method uses the Perl scripts provided with this application note. This script automatically inserts the ChipScope ICON and ILA cores into the netlist for the IP core. The second method describes manually inserting the analyzer and configuring it to capture debug data. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://www.xilinx.com/support/documentation/application_notes/xapp1002.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
