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Analog FFT interface for ultra-low power analog receiver architectures
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sadeghi, Nima Nik, Hessam M. Schlegel, Christian Gaudet, Vincent C. |
| Copyright Year | 2006 |
| Abstract | Our project is to design and implement an analog receiver including an analog decoder and a low power analog FFT processor. The FFT can be represented by a graph that is similar to the underlying graph in iterative decoders, and could potentially be implemented using comparable analog circuits with simple structures. Our system uses an OFDM with differential BPSK modulation. We simulated the system, modeled the transistors mismatch and simplified the circuit for the 256-bit FFT. Our goal is eventually to design the FFT processor in CMOS 0.18μm technology in low power subthreshold regime. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.ubc.ca/~nimas/edu/ADW06.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
