Loading...
Please wait, while we are loading the content...
Similar Documents
A Bipolar Sampled-Data Bandpass Delta-Sigma A / D Modulator
| Content Provider | Semantic Scholar |
|---|---|
| Author | Varelas, Theodore Bazarjani, Seyfi S. Snelgrove, W. Martin |
| Copyright Year | 1997 |
| Abstract | A second-order bandpass delta-sigma A/D modulator has been implemented in the bipolar subset of a 0.8μm BiCMOS process [10]. This prototype demonstrates the feasibility of a bipolar only delta-sigma modulator based on sampled data techniques. The circuit was clocked at 250 MHz and demonstrated a 40dB SNR in 1 MHz bandwidth for an input signal of 62.5 MHz. The circuit dissipates 350 mW when it operates from a 5V power supply. Introduction Digitizing a radio signal at an intermediate frequency (IF) stage of a radio receiver allows quadrature demodulation to be performed digitally eliminating any phase and amplitude imbalance between the in phase (I) and quadrature (Q) channels. Direct conversion at IF is done either by using a wide band video or ∆Σ analog to digital converter (A/D) or bandpass delta-sigma modulator (BP∆Σ). Monolithic BP∆Σ modulators have been reported that digitize signals with a bandwidth up to 200kHz, for use in GSM, IS-54, or similar radio applications. They use switched capacitor (SC) techniques [1],[2] or continuoustime circuits with off-chip inductors as resonators [3]. Increasing demand for wider bandwidth applications requires higher oversampling or higher order design to achieve the required performance. Digitizing at a higher IF is also desirable in order to simplify the radio. The SC approach has proven to be a very robust and linear technique that has a manufacturing advantage because it does not require any tuning but it has demonstrated limited speed, clocking at 10 to 100MHz. Continuous-time circuits that use -C or LC based resonators are on their way [4] [5] [6]to addressing the need for wider bandwidth A/Ds. In this paper, we present a second order BP∆Σ modulator. The modulator is designed using only npn bipolar devices. It demonstrates the feasibility and high speed of a sampled-data design style based entirely on a track and hold cell. Architectures for Bandpass Σ∆ modulator A second-order modulator is the simplest circuit that demonstrates bandpass operation, and so is useful to test new circuits and structures. It has limited linearity, though enough for radio receivers that include good filtering and low-speed AGC. The second order ∆Σ bandpass modulator noise transfer function can be derived from the first order lowpass modulator noise transfer function by mapping the zeros of the transfer function form DC to . This is achieved by a transformation. The stability and SNR characteristics of the resulting bandpass modulator will be identical to that of low pass prototype [7]. Based on this transformation the noise transfer function of the secondorder bandpass ∆Σ modulator is and the signal transfer function is . The -domain block diagram of the above second order modulator is shown in Figure 1. Note that there are two full delays from input to output and two full delays in the loop, and also note that we never have to sum more than two voltages at any node. This implementation makes possible the use of the 2-operand summer/subtracter cell described in [8] to sum the D/A feedback signal with the loop voltage.. Modulator implementation The basic building block of the modulator is a bipolar track and hold circuit. Any track and hold circuit with a 50% duty cycle holds the sampled data for half of a clock period and therefore introduces half a clock delay. We can represent this action in the z-domain by saying that the track/hold circuit has a transfer function of where A is the gain of the track/hold. Because we always use the half-delays in pairs, variation in clock timing from a 50% duty cycle is unimportant. The modulator in Figure 1 can be implemented by cascading four track/hold circuits in a master-slave configuration.The complete circuit implementation is shown in Gm f s 4 ⁄ z 1 – z 2 – – → Hq z ( ) 1 z 2 – + ( ) z 2 – ⁄ = Hs z ( ) z 2 – = |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.dissonance.com/archive/rcpapers/Varelas96.pdf |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Analog Analog-to-digital converter Architecture as Topic Automatic gain control BiCMOS Bipolar Disorder Capacitor Device Component Clock rate Clock signal Converter Device Component Delta aminolevulinate:SCnc:Pt:Urine:Qn Delta-sigma modulation Diagram Duty cycle Feedback Filter (signal processing) Gentamicins In-phase and quadrature components Intermediate frequency Low-pass filter Megahertz Node - plant part Oversampling Power supply Prototype RF modulator Radio wave Sampling - Surgical action Signal transfer function Signal-to-noise ratio Subgroup Switched capacitor voltage |
| Content Type | Text |
| Resource Type | Article |
