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Efficient Implementation & Comparison of Signed Complex Multiplier on FPGA using FFT Algorithm
| Content Provider | Semantic Scholar |
|---|---|
| Author | Fande, Archana Sahu, Anil Kumar |
| Copyright Year | 2014 |
| Abstract | Various applications based on Fast Fourier Transform (FFT) such as signal and image processing requires a high computational power, plus the ability to choose the algorithm and architecture to implement it. This paper is devoted for the design of a low power complex multiplier design to reduce the hardware required to implement the FFT algorithms. This complex multiplier can also be used for any radix-N algorithms. The aim is to design and implement a complex multiplier for Radix-4 FFT, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. The maximum path delay to implement radix-4 butterfly is 11.656ns |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijsret.org/pdf/120626.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
