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5 GB / S Monolithically Integrated Clock Recovery Circuit Using PLL and 0 . 3-jjm Gate Length Quantum Well HEMT ' s
Content Provider | Semantic Scholar |
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Author | Wang, Zhi-Gong Berroth, Manfred Nowotny, Ulrich Hofmann, Peter Dr Htilsmann, Axel Kohler, Klaus Raynor, Brian Schneider, Joachim |
Copyright Year | 2014 |
Abstract | A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3~tm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V. |
File Format | PDF HTM / HTML |
Alternate Webpage(s) | http://elib.uni-stuttgart.de/bitstream/11682/8217/1/ber22.pdf |
Language | English |
Access Restriction | Open |
Content Type | Text |
Resource Type | Article |