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Making it Easy to Deploy the UVM
| Content Provider | Semantic Scholar |
|---|---|
| Copyright Year | 2013 |
| Abstract | The Universal Verification Methodology (UVM) is becoming the dominant approach for the verification of large digital designs. However, new users often express concern about the effort required to generate a complete and useful UVM testbench. But the practical experience collected in numerous OVM and UVM projects during the last few years shows a different view. The UVM is a very suitable methodology for any kind of design and implementation, i.e. ASIC and FPGA due to the availability of the UVM library and the well-defined testbench structure. This allows the automation of essential steps in employing the UVM. This article describes an UVM approach reducing testbench implementation effort, guaranteeing an early success and streamlining the processing of the test results. Depending on the number of functional interfaces and the design complexity up to 6 weeks of implementation effort or even more can be saved. A runnable UVM testbench will be handed over to the verification team at the very beginning of the project. The verification engineers have to implement only the corresponding drivers, monitors and functional coverage models. Later on the scoreboards needed have to be architected and implemented. The results of the test execution are processed by scripts giving the project manager a continuous figure about the project status and progress. IntroductIon The Universal Verification Methodology (UVM) is an Accellera standard. It was built on the existing OVM (Open Verification Methodology) library (code base) and contributions from the Verification Methodology Manual (VMM). The key technologies employed in the UVM are ObjectOriented Programming (OOP) and Transaction-LevelModeling (TLM). They give this approach a high flexibility, raising the abstraction level and enable plug & play reuse. But they are completely new to all hardware designers and most verification engineers. This might be the main reason why UVM is considered to be useful for large ASIC designs only. But the industrial experience shows this is not true. The UVM provides best prerequisites to be employed independently of the design complexity and their silicon implementation. It is not limited to ASICs, but also very useful for FPGAs. The question is how to make the employment of UVM most effective. The UVM library can be considered as a big, but wellstructured construction set for testbench generation as well as sequence and test implementation. The UVM User Guide and additional documents like the UVM Cookbook provide rules, recommendations and examples how to use the single components of the UVM library best. Due to the structured approach of the UVM library the main architecture of an UVM testbench looks always the same. It is based on agents or sub-environments for each functional interface of the design-under-test (DUT). But each agent has the same structure. It consists of 4 blocks: a sequencer, a driver, a monitor and a coverage collector. The complete testbench consists of several agents or sub-environments, instantiated in a top-environment. This uniformity allows the automation of the generation of a complete UVM framework. This article describes an approach speeding-up the testbench generation and making the project startup easy. Making it Easy to Deploy the UVM by Dr. Christoph Sühnel, frobas GmbH |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-9_issue-2/articles/stream/making-it-easy-to-deploy-the-uvm_vh-v9-i2.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
