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Design-for-delay-testability techniques for high-speed digital circuits
| Content Provider | Semantic Scholar |
|---|---|
| Author | Vermaak, Hermanus Jacobus |
| Copyright Year | 2005 |
| Abstract | The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is getting more and more important |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://doc.utwente.nl/57440/1/thesis_Vermaak.pdf |
| Alternate Webpage(s) | http://eprints.eemcs.utwente.nl/20043/01/thesis_Vermaak.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
