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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wang, Laung-Terng Wu, Cheng-Wen Wen, Xiaoqing |
| Copyright Year | 2006 |
| Abstract | This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://booksite.elsevier.com/samplechapters/9780123705976/Sample_Chapters/01~Frontmatter.pdf |
| Alternate Webpage(s) | https://goldsandwasne.files.wordpress.com/2015/07/vlsi-test-principles-and-architectures-design-for-testability-solution-manual-pdf.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
