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An Integrated Task Graph Partitioning and Rtl Design Space Exploration System for Multi-fpga Architectures Accpted for Presentation at Fccm 99 an Integrated Task Graph Partitioning and Rtl Design Space Exploration System for Multi-fpga Architectures
| Content Provider | Semantic Scholar |
|---|---|
| Author | Srinivasan, Vinoo Vemuri, Ranga |
| Copyright Year | 1999 |
| Abstract | This paper presents spade, an integrated partitioning and register transfer level (rtl) design space exploration system for multi-fpga reconngurable architectures. The input to spade is an acyclic task graph, T G = (T; E), where T is the set of tasks and E is the set of edges. Tasks represent behavioral or algorith-mic code segments. Edges denote data dependencies between tasks. Each task is pre-synthesized to obtain a set of equivalent rtl implementations that correspond to various area-time trade-oo points in the design space of the task. spade partitions the tasks across fpgas and also selects an rtl implementation for each task such that the throughput of the task graph is maximized without violating the architectural constraints posed by the multi-fpga board. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization heuristic. The paper provides detailed description of all components in spade. We propose a novel genetic algorithm based iterative partitioning engine for spade. Results illustrate the eeectiveness of our system on several task graphs of varying sizes. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.uc.edu/~ddel/publications/srinivasan-fccm-99-submitted.ps |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
