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Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA
| Content Provider | Semantic Scholar |
|---|---|
| Author | Heydarzadeh, Siavash Kadivarian, A. Torkzadeh, Pooya |
| Copyright Year | 2012 |
| Abstract | Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx and modelsim uses for showing results. Keywords—Analog to digital converter, Successive approximation, Capacitor switching algorithm, FPGA |
| Starting Page | 927 |
| Ending Page | 930 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| Volume Number | 6 |
| Alternate Webpage(s) | http://waset.org/publications/10748/implemented-5-bit-125-ms-s-successive-approximation-register-adc-on-fpga |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
