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Workload Dependent Nbti and Pbti Aging Analysis for a Sub-45nm Commercial 3a.2 Interplay between Statistical Reliability and Variability: a Comprehensive Transistor-to- Circuit Simulation Technology, 3a.4 Defect-based Methodology for Workload-dependent Circuit Lifetime Projections – Application
| Content Provider | Semantic Scholar |
|---|---|
| Author | Chandra, Vikas Pietromonaco, David Aitken, Robert C. Dutton, Robert |
| Copyright Year | 2013 |
| Abstract | This paper analyzes aging effects in various design hierarchies of a sub-45nm commercial processor running real-world applications. Dependencies of aging effects on workloads switching-activity and power-state are quantified. This paper presents an “instance-based” simulation flow, where a unique standard-cell library is created for each instance in the design, by aging its transistors individually. Implementation results show that processor timing degradation can vary from 2%-11%, depending on workload. This paper also presents self-tuning optimization results. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://irps.org/program/technical-program/13-wed.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
