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Models for delay estimation taking into account both cross-talk and wire resistance for timing analysis
| Content Provider | Semantic Scholar |
|---|---|
| Author | Avot, Grégoire Louerat, Marie-Minerve |
| Copyright Year | 2001 |
| Abstract | While transistor gate lengths are continuously decreasing, signal inter-coupling capacitance are increasing with respect to substrate capacitance. One of the important effects of this parasitic capacitance is the modification of the signal propagation time which becomes dependant on coupling signals. In this paper, we present different methods which allow to estimate worst case delay in function of coupling signal transient periods. These estimations are intended to be used during timing analysis of circuits with large number of transistors (several millions). A special care has been taken in order to minimize CPU time and data storage size. In addition, it is also very important to take into account wire resistance in recent technologies. Our estimations allow to account for these resistance in RC trees. |
| Starting Page | 377 |
| Ending Page | 382 |
| Page Count | 6 |
| File Format | PDF HTM / HTML |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
