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CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices
| Content Provider | Semantic Scholar |
|---|---|
| Author | González, Alejandro Fernández-Montes Bhattacharya, Mayukh Kulkarni, Shriram Mazumder, Pinaki |
| Copyright Year | 2001 |
| Abstract | This paper presents a fully integrated implementation of a multivalued-logic signed-digit full adder (SDFA) circuit using a standard 0.6-/spl mu/m CMOS process. The radix-2 SDFA circuit, based on two-peak negative-differentiaI-resistance (NDR) devices, has been implemented using MOS-NDR, a new prototyping technique for circuits that combine MOS transistors and NDR devices. In MOS-NDR, the folded current-voltage characteristics of NDR devices such as resonant-tunneling diodes (RTDs) are emulated using only nMOS transistors. The SDFA prototype has been fabricated and correct function has been verified. With an area of 123.75 by 38.7 /spl mu/m/sup 2/ and a simulated propagation delay of 17 ns, the MOS-NDR prototype is more than 15 times smaller and slightly faster than the equivalent hybrid RTD-CMOS implementation. |
| Starting Page | 924 |
| Ending Page | 932 |
| Page Count | 9 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/4.924855 |
| Volume Number | 36 |
| Alternate Webpage(s) | http://web.eecs.umich.edu/~mazum/PAPERS-MAZUM/MOS-NDR.pdf |
| Alternate Webpage(s) | http://web.eecs.umich.edu/~mazum/PAPERS-MAZUM/32_SignedDigitAdder.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/4.924855 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
