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VFAT 2 : A front-end system on chip providing fast trigger information , digitized data storage and formatting for the charge sensitive readout of multi-channel silicon and gas particle detectors
| Content Provider | Semantic Scholar |
|---|---|
| Author | Aspell, P. Anelli, Giovanni Chalmet, P. Kapłon, Jan Kloukinas, Kostas Mugnier, H. Snoeys, W. |
| Copyright Year | 2008 |
| Abstract | The architecture, key design parameters and results for a highly integrated front-end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components. VFAT2 contains very low noise 128 channel front-end amplification with programmable internal calibration, intelligent “fast OR” trigger building outputs, digital data tagging and storage, data formatting and data packet transmission with error protection. VFAT2 is designed to work in the demanding radiation environments posed by modern H.E.P. experiments and in particular the TOTEM experiment of the LHC. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://wiki.iac.isu.edu/images/0/09/VFAT2_P_Aspell_9-3-07.pdf |
| Alternate Webpage(s) | https://wiki.iac.isu.edu/images/3/36/P292.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |