NDLI: METHOD FOR GENERATING TEST SIGNALS FOR AN INTEGRATED CIRCUIT AND TEST LOGIC UNIT BACKGROUND OF THE INVENTION Field of the Invention

Content Provider	Semantic Scholar
Author	Tokar, Michael
Copyright Year	2017
Abstract	(54) METHOD FOR GENERATING TEST 5,517,455 A * 5/1996 McClure et al. .............. 326/38 SIGNALS FOR AN INTEGRATED CIRCUIT 6,032,282 A 2/2000 Masuda et al. ....... ... 714/738 AND TEST LOGIC UNIT 6,058,057 A * 5/2000 Ochiai et al. ............... 365/201 6,605.956 B2 * 8/2003 Farnworth et al. ............ 326/38 (75) Inventors: Volker Kilian, München (DE); Richard Roth, Unterhaching (DE) (73) Assignee: Infineon Technologies AG, Munich (DE) (*) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 49 days.
File Format	PDF HTM / HTML
Alternate Webpage(s)	https://patentimages.storage.googleapis.com/31/85/89/70537391b211fe/US6870392.pdf
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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